1. Field of the Invention
The present invention relates generally to a fabrication process for a semiconductor device, and more particularly to a fabrication process for a semiconductor memory device.
2. Description of the Related Art
A memory cell consisted of one transistor and one capacitor as a memory cell for a high density semiconductor memory, which will be hereinafter simply referred to as "memory cell", has been widely employed for small number of components and for ease of reduction of a memory cell area.
As is well known, the output voltage of such memory cell is proportional to a capacity of the capacitor. Therefore, in order to assure stable operation at reduced size and increased package density of the memory cells, it is required to provide sufficient capacity for the capacitor. As the conventional capacitor of this type, there is a memory cell and fabrication process therefor disclosed in IEEE TRANSACTIONS OF ELECTRON DEVICES Vol. 38, 1991, pp 255 to 261.
FIG. 1J shows the construction disclosed in the above-identified IEEE paper. On the surface of a silicon substrate 301 defined with a field oxide layer 302, a gate electrode 304 is provided via a gate oxide layer 303. A source (or drain) region 305 and a drain (or source) region 306 are provided at both sides of the gate electrode 304. On the surface of an insulation layer 307 covering the gate electrode 304, the source region 305 and the drain region 306, a multi-cylindrical electrode 320 connected to the source region 305 is formed. A capacitor is formed by forming an upper electrode 319 via a multi-cylindrical type capacitor insulation layer 318 (dielectric layer) covering the multi-cylindrical electrode 320.
The multi-cylindrical type capacitor having the construction as set forth above is fabricated through the processes as illustrated in FIGS. 1A to 1J.
At first, as shown in FIG. 1A, the field oxide layer 302 is formed on the P-type silicon substrate 301 by selective oxidation, so-called LOCOS method. Then, the gate electrode 304 of a conductive polycrystalline silicon layer is formed via the gate oxide layer 303 by way of chemical vapor deposition (CVD) method. Then, by ion implantation, the source region 305 and the drain region 306 or vice versa are formed. Over the surfaces of the gate electrode 304, the source region 305 and the drain region 306, the insulation layer 307 in a thickness of approximately 300 nm of silicon oxide layer is formed. Subsequently, by the CVD method, a silicon nitride layer 308 is deposited over the insulation layer 307.
As shown in FIG. 1B, a thick silicon oxide layer 309 is deposited over the silicon nitride layer 308 by way of the CVD method. Then, an opening 307a reaching the source region 305 is formed through the first silicon oxide layer 309, the silicon nitride layer 308, the insulation layer 307.
Then, as shown in FIG. 1C, a conductive first polycrystalline silicon layer 310 is formed on the surface including the peripheral surface of the opening 307a is deposited by the CVD method. Thereafter, as shown in FIG. 1D, by way of the CVD method, a second silicon oxide layer 311 is formed over the surface of the first polycrystalline silicon layer 310. By anisotropic etching of the second silicon oxide layer 311, a first spacer 312 is formed at the side surface of the opening 307a, as shown in FIG. 1E. Subsequently, over the entire surface including the surface of the first spacer 312, a conductive second polycrystalline silicon layer 313 is deposited by way of the CVD method.
At this condition, as shown in FIG. 1F, a thick third silicon oxide layer 314 is deposited to cover the vertical portion of the second polycrystalline silicon layer 313 by the CVD method.
Next, dry etching for the third silicon oxide layer 314 is performed to maintain the third silicon oxide layer 314 only on the vertical portion of the second polycrystalline silicon layer 313 to bury so that it should not be left on the surface portion. By this process, a second spacer 316 is formed as shown in FIG. 1G.
At this condition, anisotropic etching is performed for etching back the first and second polycrystalline silicon layers 310 and 313 to remove and to form a first cylindrical electrode 316 with the first polycrystalline silicon layer 310 and a second cylindrical electrode 317 with the second polycrystalline silicon layer 313. Also, the upper portion of the first and second spacers 312 and 315 are exposed as shown in FIG. 1H.
Next, as shown in FIG. 1I, wet etching is simultaneously performed with employing hydrofluoric acid solution for the first and second spacers 312, 315 and the first silicon oxide layer 309 for removal. By this, a multi-cylindrical lower electrode consisting of the first cylindrical electrode 316 and the second cylindrical electrode 317 are formed.
Finally, over the entire surfaces of the first and second cylindrical electrodes 316 and 317, a capacitor insulation layer 318 is formed.
In this prior art, tantalum oxide layer (Ta.sub.2 O.sub.6 film) having higher dielectric constant than normal silicon nitride layer and the silicon oxide layer is employed as the capacitor insulation layer 318 for providing sufficient capacity for the capacitor. Therefore, a tungsten film formed by spattering is employed as the upper electrode 319.
By the fabrication process as set forth above, a desired capacity can be attained within a small memory cell area by permitting formation of the double cylindrical electrode.
The prior art illustrated and discussed in connection with FIGS. 1A to 1J, is adapted to form the multi-cylindrical structure within the opening 307a of the first oxide layer 309a formed through a photoresist process.
On the other hand, Japanese Unexamined Patent Publication No. 4-264767 discloses a fabrication process of a multi-cylindrical structure. The disclosed fabrication process will be discussed hereinafter with reference to FIGS. 2A to 2K.
The final capacitor structure has three cylindrical electrode including a first cylindrical layer 417, a second cylindrical layer 418 and a third cylindrical layer 419 in a lower electrode layer 408 to form a lower electrode, as shown in FIG. 2K. On the surface of the lower electrode, a capacitor insulation layer 421 is formed, and an upper electrode 422 is formed over the capacitor insulation layer 421.
In the fabrication process, at first, on the surface of a P-type silicon substrate 401, a field oxide layer 402 is selectively formed. In an element region, a gate electrode 404 is formed via a gate oxide layer 403. A source (or drain) region 405 and a drain (or source) region 406 are provided at both sides of the gate electrode 304. Then, an insulation layer 407 covering the gate electrode 404, the source region 405 and the drain region 406 is formed.
As shown in FIG. 2B, by employing normal photo-lithographic technique and dry etching technique, an opening 407a reaching to the source (or drain) region 405 is formed. On the entire surface including the surface of the opening 407a, a conductive polycrystalline silicon film is deposited by the CVD method to form the electrode layer 408. (FIG. 2B).
Subsequently, as shown in FIG. 2C, over the lower electrode layer 408, a silicon oxide layer is deposited by the CVD method. By performing patterning employing the normal photo-lithographic technique of the silicon oxide layer, a first spacer layer 409 is formed.
Then, as shown in FIG. 2D, a conductive first polycrystalline silicon layer 410 is formed on the first spacer layer 409 and the lower electrode layer 408 by way of the CVD method.
Next, as shown in FIG. 2E, by employing CVD method, the first silicon oxide layer 411 is deposited. Subsequently as shown in FIG. 2F, an isotropic etching is performed for the first silicon oxide layer 411 employing an RIE method to form a second spacer 412 only at the side surface of the first spacer 409.
Then, as shown in FIG. 2G, on the surface of the second polycrystalline silicon layer 413, a second silicon oxide layer 414 is deposited by way of the CVD method.
Subsequently, as shown in FIG. 2H, by employing the RIE method, anisotropic etching is performed for the second silicon oxide layer 414 to form into the configuration of a third spacer 415. Then, by employing the CVD method, a conductive third polycrystalline silicon layer 416 is formed on the surface of the second polycrystalline silicon layer 413 including the third spacer layer 415.
As shown in FIG. 2I, anisotropic etching is performed by the RIE method for the first, second and third polycrystalline silicon layers 410, 413 and 416 and the lower electrode layer 408, simultaneously to expose the upper portions of the first, second and third spacers 409, 412 and 415. By this, the first, second and third cylindrical electrodes 417, 418 and 419 as the lower electrode are formed and the lower electrode 408 is thus formed.
Subsequently, the first, second and third spacers 409, 412 and 415 are removed by way of wet etching employing a hydrofluoric acid solution to obtain the structure as illustrated in FIG. 2J.
Finally, as shown in FIG. 2K, over the entire surfaces of the first, second and third cylindrical electrodes 417, 418 and 419 which are exposed as set forth above and the lower electrode layer 408, a capacitor insulation layer 421 formed of a silicon nitride layer is formed. Over the entire surface of the silicon nitride layer 421, an upper electrode 422 of the conductive polycrystalline silicon is deposited by the CVD method.
Through the fabrication process set forth above, the triple cylindrical electrode can be formed.
However, in the foregoing method, when a greater capacity is desired to be provided for the small memory cell and thus greater number of cylindrical electrodes than the triple cylindrical electrode, it becomes inherent to reduce the size of the first spacer 409 as a core of the first cylindrical electrode 417, to make the layer thicknesses of respective cylindrical layers thinner and/or to reduce the clearances between respective cylindrical electrodes.
When the cross-sectional area of the first spacer 409 is reduced, a pattern may be deformed in the patterning step causing difficulty in the formation of the first spacer 409 through etching process. Also, the configuration of the first spacer 409 becomes a somewhat tapered configuration. Such a tapered configuration is not suitable configuration for performing RIE anisotropic etching for forming the first cylindrical electrode 417 as the side wall of the first spacer. In particularly, for a multi-cylindrical structure, the taper may be increased at the outer side electrode to make the formation of the side wall when the cylindrical electrode is formed utilizing the side wall formed by the inner side spacer layer. It is thus possible that formation of the side wall per se becomes impossible at a significant taper angle to make fabrication of the cylindrical electrodes impossible.
For instance, in case of a 64 Mbit class DRAM having design dimensions of 0.35 .mu.m has been considered to be limited at the triple-cylindrical structure as in the prior art set forth above. On the other hand, when a plurality of cylindrical electrodes are formed sequentially, it is likely that the thickness of the electrode at an outer side becomes greater and the height thereof becomes lower at the outer side electrode. Therefore, contribution for the effective capacity becomes smaller at the outer cylindrical electrode thereby degrading the effect of the multi-cylindrical structure.
In case of the first discussed prior art illustrated and discussed in connection with FIGS. 1A to 1J, the spacer portion (to be employed as the spacer for forming the inner first cylindrical electrode 316) illustrated as the first silicon oxide layer 309 in FIG. 1B is formed with the cylindrical electrode at the inside thereof so as not to be used as the capacity portion. Therefore, the first silicon oxide layer 309, i.e. the space portion, serves as a dead space not to be used as the capacity portion.
Also, in the case where the spacer is provided inside of the cylindrical electrode, there is a limit for down-sizing the space to obtain a suitable cylindrical electrode configuration. Therefore, the number of cylinders to form the multi-cylinder construction is limited.
Furthermore, the problem that, in the multi-cylindrical structure, the outer side cylindrical electrode has lower height than the inner side cylindrical electrode is inherent.